The present invention generally relates to a structure for minimizing floating body effects in silicon on insulator (SOI) technology utilizing a Schottky diode and a method of forming the same.
SOI technology is becoming an increasingly important field in the manufacture of integrated circuits. SOI technology deals with forming transistors in a layer of semiconductor material which overlies an insulating layer. The insulating layer is formed on an underlying substrate. The transistor comprises source and drain regions implanted into the semiconductor material. A gate structure is formed on the semiconductor material between the source and drain regions. The source and drain regions are typically formed deep into the semiconductor material and reach the insulating layer. A part of the semiconductor material isolated between the source and drain regions and underlying the gate structure is referred to as the body of the transistor. Due to the difficulty of forming a body contact, the body of the transistor in SOI is typically left electrically floating. A floating body can sometimes adversely affect the characteristics of the transistor. For example, when a high voltage is applied on the drain of the transistor, there is a charge accumulation in the body. Normally, in bulk transistors, the charge accumulation is carried away by having the wafer grounded. However, in SOI, the body is isolated by the insulating layer so a charge accumulates in the body area. As a result, a lateral bipolar transistor is formed with the source acting as the emitter and the body acting as the base. When a positive voltage is applied to the drain, a positive charge accumulates in the body. A diode formed by the junction of the source and body will turn on at a certain voltage. At this voltage, the current conducted through the transistor begins to increase exponentially. Thus, as the voltage on the drain is gradually increased, at a certain voltage, for example about 2.5 volts, the current through the transistor will begin to increase exponentially.
Although there is some conduction of current through the diode formed by the body and the source, the conduction is not enough to remove all the charge accumulating in the body. In essence, there is a race between the amount of current drawn off from the body by the source and the amount of charge accumulated in the body as a result of the high voltage applied to the drain.
This characteristic of SOI technology may cause difficulty during burn-in of a chip. Burn-in of a chip refers to the practice of operating the chip at an elevated voltage in order to test it. For example, if a chip is designed to operate at 1.8 volts, a voltage approximately 1.5 times the operating voltage, that is approximately 2.7 volts, is applied to the chip during burn-in. This is done so if any incipient defects exist in the transistor, the transistor will fail during bum-in and not during operation in the field. However, due to the above described tendency of the body to accumulate charge, the transistor may not be able to accommodate the higher burn-in voltage. Thus, there is a need to accelerate the amount of charge removed from the body to the source in order to keep the charge of the body low. This will then allow the diode to operate normally during burn-in.
A field effect transistor (FET) on an SOI substrate and method of forming the same is provided. An SOI substrate having a silicon base substrate, an insulating layer on the base substrate, and a semiconductor material on the insulating layer is provided. A conductive gate is formed on the semiconductor material. First spacers are formed on sidewalls of the gate and on the semiconductor material. Diffusion extensions are formed in the semiconductor material adjacent to and extending under a part of the gate. Second spacers are then formed on the first spacers and on the semiconductor material. Deep diffusions are implanted into the semiconductor material. The deep diffusions are implanted adjacent to the second spacers, close to the insulating layer and abutting the diffusion extensions. The semiconductor material between the deep diffusions defines a body region of the FET. At least a part of one of the second spacers is removed from the first spacers on the sidewall of the gate to expose a portion of the diffusion extension in the semiconductor material. A metal layer is formed in the semiconductor material at least in the exposed portion of the diffusion extension.